Generally, electrochemical deposition processes are used in modern integrated circuit fabrication. Metal line interconnections drive a need for increasingly sophisticated electrodeposition processes and plating tools. Much sophistication has evolved in response to a need for ever smaller current carrying lines in device metallization layers. These lines are formed by electroplating metal into very thin, high-aspect ratio trenches and vias.
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally and colloquially as wafer level packaging (WLP) and electrical connection technology. These technologies present their own very significant challenges due in part to the generally smaller feature sizes and low aspect ratios.
It is important that with the smaller feature sizes and finer pitches, an amount of electrical conductivity provided by the features is not compromised. It is in this context that embodiments described in the present disclosure arise.